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rev: 1.06 7/2002 1/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. preliminary gs840f18/32/36at-8/8.5/10/12 256k x 18, 128k x 32, 128k x 36 4mb sync burst srams 8 ns?12 ns 3.3 v v dd 3.3 v and 2.5 v i/o tqfp commercial temp industrial temp features ? flow through mode operation ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? default to interleaved pipelined mode ? byte write (bw ) and/or global write (gw ) operation ? common data inputs and data outputs ? clock control, registered, address, data, and control ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec standard 100-lead tqfp functional description applications the gs840f18/32/36a is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous sram with a 2- bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications, ranging from dsp main store to networking chip set support. the gs840f18/32/36a is available in a jedec standard 100-lead tqfp package. controls addresses, data i/os, chip enables (e 1 , e 2 , e 3 ), address burst control inputs (adsp , adsc , adv ) and write control inputs (bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable (g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order (lbo ) input. the burst function need not be used. new addresses can be loaded on every cycle with no degradation of chip performance. designing for compatibility the jedec standard for burst rams calls for a ft mode pin option (pin 14 on tqfp). board sites for flow through burst rams should be designed with v ss connected to the ft pin location to ensure the broa dest access to multiple vendor sources. boards designed with ft pin pads tied low may be stuffed with gsi?s pipeline/flow through-configurable burst rams or any vendor?s flow through or configurable burst sram. bumps designed with the ft pin location tied high or floating must employ a non-configurable flow through burst ram, like this ram, to achieve flow through functionality. byte write and global write byte write operation is performed by using byte write enable (bw ) input combined with one or more individual byte write signals (bx ). in addition, global write (gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs840f18/32/36a operates on a 3.3 v power supply and all inputs/outputs are 3.3 v- and 2.5 v-compatible. separate output power (v ddq ) pins are used to decouple output noise from the internal circuit. -8 -8.5 -10 -12 unit flow through 2-1-1-1 t kq tcycle i dd 8 9.1 115 8.5 10 105 10 10 105 12 15 80 ns ns ma
rev: 1.06 7/2002 2/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 gs840f18a 100-pi n tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 v dd nc v ss dq b5 dq b6 v ddq v ss dq b7 dq b8 dq b9 v ss v ddq v ddq v ss dq a8 dq a7 v ss v ddq dq a6 dq a5 v ss nc v dd zz dq a4 dq a3 v ddq v ss dq a2 dq a1 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc nc a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 nc nc b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 256k x 18 top view dq a9 a 17 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.06 7/2002 3/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 gs840f32a 100-pi n tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc nc a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 128k x 32 top view dq b5 nc dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 nc dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 nc dq c5 nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.06 7/2002 4/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 gs840f36a 100-pi n tqfp pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c4 dq c3 v ss v ddq dq c2 dq c1 v dd nc v ss dq d1 dq d2 v ddq v ss dq d3 dq d4 dq d5 v ss v ddq v ddq v ss dq b4 dq b3 v ss v ddq dq b2 dq b1 v ss nc v dd zz dq a1 dq a2 v ddq v ss dq a3 dq a4 v ss v ddq lbo a 5 a 4 a 3 a 2 a 1 a 0 nc nc v ss v dd nc nc a 10 a 11 a 12 a 13 a 14 a 16 a 6 a 7 e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a 8 a 9 a 15 128k x 36 top view dq b5 dq b9 dq b7 dq b8 dq b6 dq a6 dq a5 dq a8 dq a7 dq a9 dq c7 dq c8 dq c6 dq d6 dq d8 dq d7 dq d9 dq c5 dq c9 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc
rev: 1.06 7/2002 5/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 tqfp pin description pin location symbol type description 37, 36 a 0 , a 1 i address field lsbs and address counter preset inputs 35, 34, 33, 32, 100, 99, 82, 81,44, 45, 46, 47, 48, 49, 50 a 2 ?a 16 i address inputs 80 a 17 i address inputs (x18 versions) 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79 2, 3, 6, 7, 8, 9, 12, 13 18, 19, 22, 23, 24, 25, 28, 29 dq a1 ?dq a8 dq b1 ?dq b8 dq c1 ?dq c8 dq d1 ?dq d8 i/o data input and output pins (x32, x36 version) 51, 80, 1, 30 dq a9 , dq b9 , dq c9 , dq d9 i/o data input and output pins (x36 version) 51, 80, 1, 30 nc ? no connect (x32 version) 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 dq a1 ?dq a9 dq b1 ?dq b9 i/o data input and output pins (x18 version) 51, 52, 53, 56, 57 75, 78, 79 1, 2, 3, 6, 7 25, 28, 29, 30 nc ? no connect (x18 version) 87 bw i byte write?writes all enabled bytes; active low 93, 94 b a , b b i byte write enable for dq a , dq b data i/os; active low 95, 96 b c , b d i byte write enable for dq c , dq d data i/os; active low (x32, x36 version) 95, 96 nc ? no connect (x18 version) 89 ck i clock input signal; active high 88 gw i global write enable?writes all bytes; active low 98, 92 e 1 , e 3 i chip enable; active low 97 e 2 i chip enable; active high 86 g i output enable; active low 83 adv i burst address counter advance enable; active low 84, 85 adsp , adsc i address strobe (processor, ca che controller); active low 64 zz i sleep mode control; active high 31 lbo i linear burst order mode; active low 15, 41, 65, 91 v dd i core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90 v ss i i/o and core ground 4, 11, 20, 27, 54, 61, 70, 77 v ddq i output driver power supply 14, 16, 38, 39, 42, 43, 66 nc ? no connect
rev: 1.06 7/2002 6/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 gs840f18/32/36a block diagram a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0?an lbo adv ck adsc adsp gw bw b a b b b c b d e 1 g zz power down control memory array 36 36 4 a qd e 3 e 2 dqx0?dqx9 note: only x36 version shown for simplicity. 1 0
rev: 1.06 7/2002 7/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 note: there is a are pull-up devices on the lbo and ft pins and a pull-down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. burst counter sequences byte write truth table notes: 1. all byte outputs are active in read cycles regar dless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c, and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x32 and x36 versions. mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb function gw bw b a b b b c b d notes read h h x x x x 1 read hlhhhh1 write byte a hl lhhh2, 3 write byte b hlhlhh2, 3 write byte c h l h h l h 2, 3, 4 write byte d hlhhhl2, 3, 4 write all byteshlllll2, 3, 4 write all byteslxxxxx linear burst sequence note: the burst counter wraps to initial state on the 5th clock. i nterleaved burst sequence note: the burst counter wraps to initial state on the 5th clock. a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00
rev: 1.06 7/2002 8/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low. 2. e = t (true) if e 2 = 1 and e 3 = 0; e = f (false) if e 2 = 0 or e 3 = 1. 3. w = t (true) and f (false) is defined in the byte write truth table preceding. 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above.
rev: 1.06 7/2002 9/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr simplified state diagram notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assu mes active use of only the enable (e 1, e 2, e 3 ) and write (b a , b b , b c , b d , bw , and gw ) control inputs, and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write, and adsc control inputs, and assumes adsp is tied high and adv is tied low.
rev: 1.06 7/2002 10/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw simplified state diagram with g notes: 1. the diagram shows supported (tes ted) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads ? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time.
rev: 1.06 7/2002 11/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. notes: 1. unless otherwise noted, all performance specificati ons quoted are evaluated for worst case at both 2.75 v v ddq 2.375 v (i.e., 2.5 v i/o) and 3.6 v v ddq 3.135 v (i.e., 3.3 v i/o) and quoted at whichever condition is worst case. 2. this device features input buffers compat ible with both 3.3 v and 2.5 v i/o drivers. 3. most speed grades and configurations of this device are offer ed in both commercial and industrial temperature ranges. the pa rt number of industrial temperature range versions end t he character ?i?. unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. input under/overshoot voltage must be ?2 v > vi < v dd +2 v with a pulse width not to exceed 20% tkc. absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 4.6 v v ddq voltage in v ddq pins ?0.5 to v dd v v ck voltage on clock input pin ?0.5 to 6 v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ?0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/?20 ma i out output current on any i/o pin +/?20 ma p d package power dissipation 1.5 w t stg storage temperature ?55 to 125 o c t bias temperature under bias ?55 to 125 o c recommended oper ating conditions parameter symbol min. typ. max. unit notes supply voltage v dd 3.135 3.3 3.6 v i/o supply voltage v ddq 2.375 2.5 v dd v1 input high voltage v ih 1.7 ? v dd +0.3 v2 input low voltage v il ?0.3 ? 0.8 v 2 ambient temperature (commercial range versions) t a 02570 c3 ambient temperature (industrial range versions) t a ?40 25 85 c3
rev: 1.06 7/2002 12/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 note: this parameter is sample tested. notes: 1. junction temperature is a function of sr am power dissipation, package thermal resi stance, mounting board temperature, ambient . temper- ature air flow, board density, and pcb thermal resistance. 2. scmi g-38-87. 3. average thermal resistance between die and top surface, mil spec-883, method 1012.1. 4. for x18 confi guration, consult factory. capacitance (t a = 25 o c, f = 1 mh z , v dd = 3.3 v) parameter symbol test conditions typ. max. unit control input capacitance c i v dd = 3.3 v 34pf input capacitance c in v in = 0 v 45pf output capacitance c out v out = 0 v 67pf package thermal characteristics rating layer board sym bol tqfp max unit notes junction to ambient (at 200 lfm) single r ja 40 c/w 1,2,4 junction to ambient (at 200 lfm) four r ja 24 c/w 1,2,4 junction to case (top) r jc 9 c/w 3,4 20% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd +? 2.0 v 50% v dd v il
rev: 1.06 7/2002 13/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 notes: 1. include scope and jig capacitance. 2. test conditions as specified wi th output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz , and t ohz . 4. device is deselected as defined by the truth table. ac test conditions parameter conditions input high level 2.3 v input low level 0.2 v input slew rate 1 v/ns input reference level 1.25 v output reference level 1.25 v output load fig. 1& 2 dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ?1 ua 1 ua zz input current i inzz v dd v in v ih 0v v in v ih ?1 ua ?1 ua 1 ua 300 ua mode pin input current i inm v dd v in v il 0v v in v il ?300 ua ?1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?4 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh i oh = ?4 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 4 ma ? 0.4 v dq vt = 1.25 v 50 ? 30pf * dq 2.5 v output load 1 output load 2 225 ? 225 ? 5pf * * distributed test jig capacitance
rev: 1.06 7/2002 14/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 operating currents ac electrical characteristics notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above. parameter test conditions symbol -8 -8.5 -10 -12 unit 0 to 70c -40 to 85c 0 to 70c -40 to 85c 0 to 70c -40 to 85c 0 to 70c -40 to 85c operating current device selected; all other inputs v ih o r v il output open i dd flow through 115 125 105 115 105 115 80 90 ma standby current zz v dd ? 0.2 v i sb flow through 20 30 20 30 20 30 20 30 ma deselect current device deselected; all other inputs v ih or v il i dd flow through 20 30 20 30 20 30 15 25 ma parameter symbol -8 -8.5 -10 -12 unit minmaxminmaxminmaxminmax flow through clock cycle time tkc 9.1 ? 10.0 ? 10.0 ? 15.0 ? ns clock to output valid tkq ? 8.0 ? 8.5 ? 10 ? 12 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns g to output valid toe ? 3.2 ? 3.5 ? 3.8 ? 5 ns g to output in low-z tolz 1 0?0?0?0?ns g to output in high-z tohz 1 ? 3.2 ? 3.5 ? 3.8 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5?5?5?5?ns zz hold time tzzh 2 1?1?1?1?ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns
rev: 1.06 7/2002 15/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 ck adsp adsc adv gw bw g wr2 wr3 wr1 wr1 wr2 wr3 tkc single write burst write d2a d2b d2c d2d d3a d1 a t kl t kh ts th ts th ts th ts th ts th ts th ts th ts th write specified byte for 2 a and all bytes for 2 b , 2 c & 2 d adv must be inactive for adsp write adsc initiated write adsp is blocked by e 1 inactive a 0 ?an b a ?b d dq a ?dq d write deselected hi-z wr1 wr2 wr3 write cycle timing e 1 e 3 ts th ts th ts th e 2 and e 3 only sampled with adsp or adsc e 1 masks adsp e 2 deselected with e 2
rev: 1.06 7/2002 16/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 q 1a q 3a q 2d q 2c q 2b q 2a tkq tlz toe tohz tolz tkqx thz tkqx ck adsp adsc bw g gw adv burst read rd2 rd3 tkl ts th th ts th ts th adsc initiated read suspend burst single read adsp is blocked by e 1 inactive a 0 ?an b a ?b d tkh tkc ts th ts ts th dq a ?dq d rd1 hi-z suspend burst fl ow th roug h r ea d c yc l e ti m i ng e 2 ts th th th e 1 masks adsp e 2 and e 3 only sampled with adsp or adsc deselected with e 2 e 3 e 1 ts ts
rev: 1.06 7/2002 17/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 flow through read-write cycle timing ck adsp adsc adv gw bw g rd1 wr1 rd2 q1a d1a q2a q2b q2c q2d single read burst read toe tohz ts th ts th th ts th ts th ts th ts th tkh adsc initiated read dq a ?dq d b a ?b d a0?an tkl tkc ts single write adsp is blocked by e inactive tkq ts th hi-z q2a burst wrap around to it?s initial state wr1 e 1 e 3 e 2 ts ts th ts e 1 masks adsp e 2 and e 3 only sampled with adsp and adsc deselected with e 3 th th
rev: 1.06 7/2002 18/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 ck adsp adsc th tkh tkl tkc ts zz tzzr tzzh tzzs ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ snooze sleep mode timing diagram
rev: 1.06 7/2002 19/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 gs840f18/32/36a output dr iver characteristics -80 -60 -40 -20 0 20 40 60 -0.500.511.522.533.54 v out (pull dow n) vddq - v out (pull up) i out (ma) 3.6v pd ld 3.3v pd ld 3.1v pd ld 3.1v pu ld 3.3v pu ld 3.6v pu ld pull up driv ers pull down driv ers v ddq vout i out v ss
rev: 1.06 7/2002 20/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 tqfp package drawing d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity ? ? 0.10 lead angle 0 ?7
rev: 1.06 7/2002 21/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 ordering information for gsi synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 18 gs840f18at-8 flow through tqfp 8 c 256k x 18 gs840f18at-8.5 flow through tqfp 8.5 c 256k x 18 gs840f18at-10 flow through tqfp 10 c 256k x 18 gs840f18at-12 flow through tqfp 12 c 128k x 32 gs840f32at-8 flow through tqfp 8 c 128k x 32 gs840f32at-8.5 flow through tqfp 8.5 c 128k x 32 gs840f32at-10 flow through tqfp 10 c 128k x 32 gs840f32at-12 flow through tqfp 12 c 128k x 36 gs840f36at-8 flow through tqfp 8 c 128k x 36 gs840f36at-8.5 flow through tqfp 8.5 c 128k x 36 gs840f36at-10 flow through tqfp 8.5 c 128k x 36 gs840f36at-12 flow through tqfp 8.5 c 256k x 18 gs840f18at-8i flow through tqfp 8 i 256k x 18 gs840f18at-8.5i flow through tqfp 8.5 i 256k x 18 gs840f18at-10i flow through tqfp 10 i 256k x 18 gs840f18at-12i flow through tqfp 12 i 128k x 32 gs840f32at-8i flow through tqfp 8 i 128k x 32 gs840f32at-8.5i flow through tqfp 8.5 i 128k x 32 gs840f32at-10i flow through tqfp 10 i 128k x 32 gs840f32at-12i flow through tqfp 12 i 128k x 36 gs840f36at-8i flow through tqfp 8 i 128k x 36 gs840f36at-8.5i flow through tqfp 8.5 i 128k x 36 gs840f36at-10i flow through tqfp 10 i 128k x 36 gs840f36at-12i flow through tqfp 12 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs840f32at -8t. 2. the speed column indicates the cycle frequency (mhz) of the dev ice in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gs i technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
rev: 1.06 7/2002 22/22 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com . preliminary gs840f18/32/36at-8/8.5/10/12 revision history rev. code: old; new types of changes format or content page /revisions;reason gs84018/32/362/2000g; 840f18a_r1_02 content ? updated pin description table 840f18a_r1_02; 840f18a_r1_03 content/format ? added ?non-a? speed bins to operating currents table, ac electrical characteristics table, and ordering information table ? updated format to fit technical documentation standards 840f18a_r1_03; 840f18a_r1_04 content/format ? updated table on page 1 ? updated operating currents table on page 14 ? updated ac electrical char acteristics table on page 14 ? updated format to comply with present technical documentation standards 840f18a_r1_04; 840f18a_r1_05 content ? reduced i dd by 20 ma in table on page 1 and operating currents table 840f18a_r1_05; 840f18a_r1_06 content ? removed 7.5 ns references from entire datasheet

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